/*
 * reg_file.v
 *
 * Copyright 2024 dh33ex <dh33ex@riseup.net>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA or visit <http://www.gnu.org/licenses/>.
 *
 *
 */

module reg_file(
    input               i_clk,
    input               i_rst,

    input       [3:0]   i_reg1_a,
    input       [3:0]   i_reg2_a,
    input       [3:0]   i_reg3_a,

    input               i_reg1_we,
    input       [31:0]  i_reg1_wd,

    input       [31:0]  i_PC,
    input               i_lnk_trig,

    output      [31:0]  o_reg1_rd,
    output      [31:0]  o_reg2_rd,
    output      [31:0]  o_reg3_rd
);

    reg [31:0]   regs[0:15];

    always @(posedge i_clk) begin
        if (i_rst) begin
            regs[0] <= 0;
            regs[1] <= 0;
            regs[2] <= 0;
            regs[3] <= 0;
            regs[4] <= 0;
            regs[5] <= 0;
            regs[6] <= 0;
            regs[7] <= 0;
            regs[8] <= 0;
            regs[9] <= 0;
            regs[10] <= 0;
            regs[11] <= 0;
            regs[12] <= 0;
            regs[13] <= 0;
            regs[14] <= 0;
            regs[15] <= 0;
        end else if (i_reg1_we) begin
            regs[i_reg1_a] <= i_reg1_wd;
        end

        if (i_lnk_trig) begin
            regs[15] <= i_PC + 4;
        end
    end

    assign o_reg1_rd = regs[i_reg1_a];
    assign o_reg2_rd = regs[i_reg2_a];
    assign o_reg3_rd = regs[i_reg3_a];

endmodule
